1. Field of Invention
The present invention relates to a method of fabricating a liquid crystal display including the step of simultaneously forming a first storage electrode of a storage capacitor and a source/drain region in a single step of doping a semiconductor layer with impurities.
2. Discussion of Related Art
FIG. 1 shows a cross-sectional view of a liquid crystal display having a pixel array and a circuit which are formed on a common substrate according to a related art. The left portion of FIG. 1 represents the pixel array and the right portion of FIG. 1 represents the circuit.
Referring to FIGS. 1 and 2A, an active layer 11 is formed on an insulated substrate 100 of a pixel array. A source region 11S, a channel region 11C and a drain region 11D are formed in the active layer 11. Each LDD region 11L is formed between the source region 11S and the channel region 11C and between the drain region 11D and the channel region 11C. A first storage electrode 11T of a storage capacitor is formed with the drain region 11D as part of an integral body. The first storage electrode 11T, as shown in FIG. 1, is formed by doping a silicon layer used for forming an active layer heavily with either n-type or p-type impurities.
A gate electrode 13G having a gate insulating layer 12G located thereunder is disposed on the channel region 11C of the active layer 11. A second storage electrode 13T having a storage capacitor insulating layer 12T located thereunder is formed on the first storage electrode 11T. Hereinafter, an insulating layer between the first storage electrode and the second storage electrode of the storage capacitor will be referred to as a storage capacitor insulating layer.
A first insulating layer 110 having contact holes which expose the source region 11S and the drain region 11D covers an entire surface of the substrate 100. A source wire 15 connected to the source region 11S is disposed on the first insulating layer 110.
A second insulating layer 120 exposing the drain region 11D through the first insulating layer 110 covers the substrate again. A pixel electrode 17 connected to the drain region 11D is formed on the second insulating layer 120.
A circuit includes two active layers 21 and 21' for defining an n-type TFT and a p-type TFT, respectively, which layers are formed in the insulating substrate 100. Source regions 21S and 21S', channel regions 21C and 21C' and drain regions 21D and 21D' are formed in the active layers 21 and 21'. Gate electrodes 23G and 23G' having gate insulating layers 22 and 22' disposed thereunder, are formed on the channel regions 21C and 21C' of the active layers 21 and 21', respectively. The first insulating layer 110 having contact holes exposing the source regions 21S and 21S' and the drain regions 21D and 21D' covers the substrate 100.
A first wire 25-1, a second wire 25-2 and a third wire 25-3 connected to the source regions 21S and 21S' and the drain regions 21D and 21D' to provide a CMOS structure including the n-type TFT and the p-type TFT are formed on the first insulating layer 110. The second insulating layer 120 covers the surface of the substrate 100.
FIG. 2A to FIG. 2H show cross-sectional views of a method of fabricating a liquid crystal display (hereinafter abbreviated LCD) according to a related art shown in FIG. 1.
Referring to FIG. 2A, active layers 11, 21 and 21' are formed in a pixel array and a circuit via photolithography, respectively, after a polycrystalline silicon layer has been formed on an insulated substrate 100. The polycrystalline silicon layer may be formed by crystallizing an amorphous silicon layer via a laser annealing process after the amorphous silicon layer has been deposited on the insulated substrate 100.
Referring to FIG. 2B, a photoresist pattern PR exposing only a portion so as to define a first storage electrode 11T in the active layer 11 of the pixel array is provided. Then, a first storage electrode 11T is formed by heavily doping the exposed portion of the active layer with n-type impurities.
Referring to FIG. 2C, after the photoresist pattern PR has been removed, an insulating layer for forming a gate insulating layer and a first conductive layer are formed on the substrate, successively. Gate electrodes 13G, 23G and 23G' in the pixel array and the circuit and a second storage electrode 13T corresponding to the first storage electrode 11T in the pixel array are formed by removing predetermined portions of the first conductive layer via photolithography.
Then, as shown in FIG. 2D, gate insulating layers 12, 22 and 22' and a storage capacitor insulating layer 12T are formed by etching the insulating layer for providing gate insulation while using the electrodes 13G, 23G, 23G' and 13T as etching masks.
Referring to FIG. 2D, n-type lightly doped impurity regions 11A, 21A and 21A' are formed by doping the active layers 11, 21 and 21' lightly with n-type impurities, respectively. In this case, each of the gate electrodes 13G, 23G and 23G' function as doping-blocking layers against the dopants. For forming LDD regions in TFTs of the pixel array, this process has no influence on the density of impurities in the first storage electrode 11T having already been doped heavily.
Referring to FIG. 2E, a photoresist pattern PR which blocks the LDD region 11L is defined to have a predetermined size in the TFT of the pixel array and thus, the p-type TFT region of the circuit is formed. Then, source regions 11S and 21S and drain regions 11D and 21D are formed respectively in the active layer 11 of the pixel array and in the active layer 21 of the n-type TFT of the circuit by doping the substrate heavily with n-type impurities.
Referring to FIG. 2F, after a photoresist pattern PR exposing only a p-type TFT region of the circuit has been formed on the substrate, a source region 21S' and a drain region 21D' are formed in the active layer 21' of the p-type TFT of the circuit by doping the substrate heavily with p-type impurities. An n-type, lightly doped impurity region 21A' in the active layer 21' of the p-type TFT becomes a source region 21S' and a drain region 21D' by being doped heavily with p-type impurities during this process.
Referring to FIG. 2G, after the photoresist pattern has been removed, a first insulating layer 110 covering an exposed substrate is formed. Then, contact holes exposing the source regions 21S and 21S' and the drain regions 21D and 21D' of the n-type TFT and the p-type TFT in the circuit are formed. After a second conductive layer has been formed on the substrate, a source wire 15 (FIG. 2H) connected to the source region 11S in the pixel array and a first wire 25-1, a second wire 25-2 and a third wire 25-3 connecting the n-type TFT to the p-type TFT in the circuit to make a CMOS arrangement are formed respectively via photolithography.
Referring to FIG. 2H, after a second insulating layer 120 has been formed on an exposed surface of the substrate, a contact hole exposing the drain region 11D in the pixel array is formed by etching the first insulating layer 110 and the second insulating layer via photolithography. After a transparent conductive layer has been formed on the surface of the substrate, a pixel electrode 17 connected to the drain region 11D is formed via photolithography.
Unfortunately, three steps of forming photoresist patterns are required for forming the first storage electrode, source regions, drain regions and the LDD regions in the active layer, and four impurity-doping steps are also required. Accordingly, the fabricating process is extremely complicated, and it is hard to fabricate a non-defective device because of mis-aligned photoresist patterns used for photolithography.